The present invention relates to systems and methods for design verification of devices. More particularly, the present invention relates to pseudo-random testing of processors that may be used in computers or other processing machines.
During the development and manufacture of microprocessors, there is a need to exhaustively test various designs and products before release to customers. Ideally, a processor's performance is verified for all possible circumstances under which it might be operated in the real world. Unfortunately, this would involve testing a potentially infinite number of machine operation sequences and therefore require a prohibitively long time to generate and run test sequences.
To sample a wide range of possible machine operation sequences for design verification, random instruction generators were developed. These systems simply generate a random sampling of instructions (typically in the processor's assembly language) which is then converted to machine code and tested on the processor. Although such systems can provide a wide range of possible processor operations with minimal user input, they have no understanding of what operation sequences are likely to be encountered in the real world. Further, they do not understand which operation sequences might be most difficult for the microprocessor to handle. Thus, they sometimes fail to adequately test important aspects of a processor's functioning.
In an alternative approach, a human programs a sequence of test instructions for verifying the processor design. In so doing, the user makes use of his knowledge of real world situations in which the processor might be expected to encounter difficulty. This allows the programmer to design tests which he or she expects to be difficult for the processor to successfully handle. Unfortunately, each user's experience is somewhat limited. Therefore, the test code likely will not sample a sufficiently large number of situations to adequately test the processor. Further, if the programmer was to attempt to write tests encompassing a sufficiently wide range of test cases, he or she would eventually spend a prohibitively long time developing the test code.
Thus, there exists a need for a testing system that can provide both a wide range of processor operation sequences together with specific test sequences which might be expected to provide real world difficulties for a target processor.